ARM Memory Barrier 실전 — DMB·DSB·ISB·DMA·MMIO

1
shared_data = compute();
2
__DMB();
3
flag = 1;   /* shared_data write가 flag write *전*에 가시 */

1
volatile uint32_t data;
2
volatile bool ready;
3

4
/* ISR */
5
data = sample;
6
__DMB();   /* data write가 ready 변경 전 가시 보장 */
7
ready = true;
8

9
/* Task */
10
while (!ready);
11
__DMB();   /* ready read 후 data read */
12
process(data);

1
/* Clock 활성화 후 register access */
2
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
3
__DSB();   /* clock enable 완료 대기 */
4
TIM2->CR1 = 1;   /* safe */

1
fill_buffer(tx_buf, len);
2
SCB_CleanDCache_by_Addr(tx_buf, len); /* cacheable buffer라면 먼저 clean */
3
__DSB();   /* memory access 완료 순서 동기화 */
4
DMA->CR = DMA_START;   /* DMA가 fresh data 봄 */

1
/* Self-modifying code */
2
flash_write(addr, new_code);
3
SCB_CleanDCache_by_Addr(addr, size);
4
SCB_InvalidateICache_by_Addr(addr, size);
5
__DSB(); __ISB();   /* pipeline 안 *옛 명령* 클리어 */
6
call((void*)addr);

1
SCB->CPACR |= (0xF << 20);   /* FPU enable */
2
__DSB(); __ISB();   /* settle + pipeline flush */
3

4
float x = compute_fp();   /* safe */

1
__DMB();         /* full system — slowest */
2
__DMB_ISH();     /* Inner Shareable — SMP cluster 안 */
3
__DMB_NSH();     /* Non-shareable — same CPU */
4
__DMB_OSH();     /* Outer Shareable — across clusters */

1
/* Linux smp_mb() = DMB ISH */
2
smp_mb();

1
/* SMP — DMB ISH 또는 LDAR/STLR */
2

3
/* C11 atomic — 자동 처리 */
4
atomic_store_explicit(&head, next, memory_order_release);
5
                                   /* → STLR */

1
/* C 명시 barrier 버전 */
2
bool push(ring_t *r, uint8_t b) {
3
    uint16_t h = r->head;
4
    uint16_t next = (h + 1) & MASK;
5
    if (next == r->tail) return false;
6

7
    r->buf[h] = b;
8
    __DMB();   /* buf write 후 head update — release */
9
    r->head = next;
10
    return true;
11
}
12

13
bool pop(ring_t *r, uint8_t *out) {
14
    uint16_t t = r->tail;
15
    if (t == r->head) return false;
16

17
    __DMB();   /* head check 후 buf read — acquire */
18
    *out = r->buf[t];
19
    r->tail = (t + 1) & MASK;
20
    return true;
21
}

1
/* TX path */
2
fill_data(buf, len);
3
SCB_CleanDCache_by_Addr(buf, len);   /* cache → memory */
4
__DSB();
5
DMA_start(buf, len);
6

7
/* RX path */
8
DMA_start(buf, len);
9
/* DMA writes memory */
10
wait_dma_done();
11
SCB_InvalidateDCache_by_Addr(buf, len);   /* cache stale data 폐기 */
12
__DSB();
13
read_data(buf);

1
void flash_write_and_jump(uint32_t addr, uint8_t *code, size_t len) {
2
    /* 1. Write to flash */
3
    flash_unlock();
4
    flash_erase(addr);
5
    for (size_t i = 0; i < len; i += 4) {
6
        flash_program_word(addr + i, *(uint32_t*)(code + i));
7
    }
8
    flash_lock();
9

10
    /* 2. Cache maintenance */
11
    SCB_CleanInvalidateDCache_by_Addr((uint32_t*)addr, len);
12
    SCB_InvalidateICache_by_Addr((uint32_t*)addr, len);
13

14
    /* 3. Barriers */
15
    __DSB();
16
    __ISB();
17

18
    /* 4. Jump */
19
    ((void(*)())(addr | 1))();
20
}

1
SCB->VTOR = NEW_VECTOR_BASE;
2
__DSB();   /* settle */
3
__ISB();   /* pipeline flush */
4
/* 이제 IRQ가 새 vector 사용 */

1
/* Core 0 — boot core 1 */
2
core1_entry_addr = (uint32_t)core1_main;
3
__DSB();   /* entry addr write 완료 */
4
core1_wake();   /* core 1 reset release */
5

6
/* Core 1 — reset handler */
7
void core1_reset(void) {
8
    while (core1_entry_addr == 0);   /* wait */
9
    __DMB();   /* read complete */
10
    ((void(*)())core1_entry_addr)();
11
}

1
SCB->VTOR = new_addr;
2
__DMB();   /* ← 부족 — DSB·ISB 필요 */

1
flag = 1;
2
__DMB();   /* ← 너무 늦음 — flag가 이미 가시화 */
3
data = compute();

1
atomic_store(&x, 1);
2
__DMB();   /* ← atomic 자체가 acquire/release — 중복 */

1
__DMB_ISH();   /* ← Cortex-M에는 share domain 개념 없음 */