Cache Line Alignment — alignas·Padding·SoA 적용

1
/* C++17 */
2
#include <new>
3
constexpr size_t CACHE_LINE = std::hardware_destructive_interference_size;
4

5
/* Runtime */
6
long line_size = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);

1
#include <cstddef>
2
#include <atomic>
3

4
struct alignas(64) hot_data {
5
    std::atomic<int> counter;
6
};
7

8
hot_data g_data;   /* &g_data % 64 == 0 보장 */

1
struct counters {
2
    alignas(64) std::atomic<int> a;
3
    char pad_a[64 - sizeof(std::atomic<int>)];
4

5
    alignas(64) std::atomic<int> b;
6
    char pad_b[64 - sizeof(std::atomic<int>)];
7
};
8

9
static_assert(sizeof(counters) == 128, "padded counters");

1
template<typename T, size_t N>
2
struct spsc_ring {
3
    alignas(64) std::atomic<size_t> head;
4
    char pad_h[64 - sizeof(std::atomic<size_t>)];
5

6
    alignas(64) std::atomic<size_t> tail;
7
    char pad_t[64 - sizeof(std::atomic<size_t>)];
8

9
    alignas(64) T buf[N];
10
};

1
/* AoS — 한 particle을 다 fetch */
2
struct particle { float x, y, z, vx, vy, vz, mass; };
3
particle parts[N];
4

5
for (int i = 0; i < N; i++) {
6
    parts[i].x += parts[i].vx * dt;
7
    /* y, z, mass까지 같은 line에 fetch — 60% 낭비 */
8
}
9

10
/* SoA — x, vx만 fetch */
11
struct particles_soa {
12
    alignas(64) float x[N];
13
    alignas(64) float y[N];
14
    alignas(64) float vx[N];
15
    alignas(64) float vy[N];
16
};
17

18
for (int i = 0; i < N; i++) {
19
    parts.x[i] += parts.vx[i] * dt;
20
}

1
struct guest {
2
    /* Hot — 매 frame 접근 */
3
    alignas(64) int id;
4
    int active;
5
    int last_login;
6
    char pad[64 - 3 * sizeof(int)];
7

8
    /* Cold — 화면에 표시할 때만 */
9
    char email[128];
10
    char address[256];
11
};

1
struct counter_per_cpu {
2
    alignas(64) atomic_long value;
3
} per_cpu_counters[NUM_CORES];
4

5
void inc(int cpu) {
6
    atomic_fetch_add(&per_cpu_counters[cpu].value, 1);
7
}
8

9
long sum_all(void) {
10
    long s = 0;
11
    for (int i = 0; i < NUM_CORES; i++)
12
        s += atomic_load(&per_cpu_counters[i].value);
13
    return s;
14
}

1
#include <linux/cache.h>
2

3
struct foo {
4
    int a;
5
    int b ____cacheline_aligned;   /* 새 line */
6
};
7

8
static struct bar ____cacheline_aligned g_bar;

1
NEON aligned vs misaligned load (Cortex-A72)
2
aligned    vld1q_f32       1 cycle/load
3
misaligned vld1q_f32       2 cycle/load (cross-line)

1
struct foo {
2
    alignas(64) int a;
3
    int b;   /* a와 같은 line — padding 없음 */
4
};

1
void func(void) {
2
    alignas(64) int x;   /* stack은 16/32B만 보장하는 경우 많음 */
3
}

1
/* Cortex-M7 line = 32 B */
2
alignas(64) int x;   /* 메모리 두 배 낭비 */

1
struct {
2
    char c;
3
    int i;
4
} __attribute__((packed));   /* i가 misaligned → Cortex-M0/ARMv6 fault */

1
uint8_t buf[1024];   /* alignment 1 — neighbor line 영향 */
2
SCB_CleanDCache_by_Addr((uint32_t*)buf, 1024);